1. Technical Field
Embodiments of the invention are generally related to memory management, and more particularly to the control of memory refresh operations.
2. Background Art
With advances in computing technology, computing devices are smaller and have much more processing power. Additionally, they include more and more storage and memory to meet the needs of the programming and computing performed on the devices. The shrinking size of the devices together with the increased storage capacity is achieved by providing higher density devices, where the atomic storage units within a memory device have smaller and smaller geometries.
With successive generations of increasingly dense memory devices, intermittent failures have become more frequent. For example, some existing DDR3 based systems experience intermittent failures with heavy workloads. Researchers have traced the failures to repeated access to a single row of memory within the refresh window of the memory cell. For example, for a 32 nm process, if a row is accessed 550K times or more in the 64 millisecond refresh window, the physically adjacent wordline to the accessed row has a very high probability of experiencing data corruption. The row hammering or repeated access to a single row can cause migration across the passgate. The leakage and parasitic currents caused by the repeated access to one row cause data corruption in a non-accessed physically adjacent row. The failure issue has been labeled as a ‘row hammer’ or ‘row disturb’ issue by the DRAM industry where it is frequently seen.
Recently, targeted row refresh technologies have been introduced to mitigate the effects of row hammering. Various operations to facilitate targeted row refreshes tend to complicate the timing of other processes in a memory subsystem. As memory technologies continue to scale, it is expected that reliance on targeted row refresh techniques increase. This increased reliance poses a challenge to protecting the performance of DRAM and other types of memory systems.